`timescale 1ns/1ps

module tb_t_pwm();

reg sys_clk = 1'b0;
reg sys_rst_n;
wire out_pulse;

t_pwm#(.CNT_MAX(17'd10_000)) u_t_pwm(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    .out_pulse(out_pulse)
);

always #10 sys_clk = ~sys_clk;

initial begin
    sys_rst_n <= 1'b0;
    #100
    sys_rst_n <= 1'b1;
end


endmodule